比特派10官网下载|wafers

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2024-03-08 20:36:05

高科技之半导体硅片概念硅片（又称晶圆、wafer）是光伏、半导体行业广泛使用的基础材料。其中，适用于集成电路行业的是半导体级的硅片半导... - 雪球

半导体硅片概念

硅片（又称晶圆、wafer）是光伏、半导体行业广泛使用的基础材料。其中，适用于集成电路行业的是半导体级的硅片

半导... - 雪球首页行情行情中心筛选器新股上市买什么交易A股交易基金交易私募中心下载App扫一扫，下载登录/注册大九先生()发布于2018-08-03 23:55来自雪球关注高科技之半导体硅片来源：雪球App，作者：大九先生，（https://xueqiu.com/3864375431/111584172）概念硅片（又称晶圆、wafer）是光伏、半导体行业广泛使用的基础材料。其中，适用于集成电路行业的是半导体级的硅片半导体硅片对产品质量及一致性要求极高，其纯度须达99.9999999%（9个9）以上，而最先进的工艺甚至需要做到99.999999999%（11个9）。而光伏级单晶硅片仅需5个9即可满足应用需求。所以半导体生产所用硅片的制备难度远大于光伏级硅片在半导体上游材料市场中，硅片成本占比最高，同时市场规模保持高速增长。2017年硅片市场规模达86.8亿美元（32%市场占比），远高于气体和光掩膜市场规模；在2015-2017期间，硅片市场规模CAGR约为4.61%，高于同期半导体整体市场增长速度分类用途 1.按尺寸分： 50mm（2寸）、100mm（4寸）、125mm（5寸）、150mm（6寸）、200mm（8寸）、300mm（12寸）、450mm 300mm硅棒大约1m长，并需要在坩埚中融化150kg—300kg的半导体级硅。硅片直径的增加可以摊薄生产成本。300mm硅片比200mm硅片面积提升2.25倍，一个硅片上可以生产更多硅片，每个芯片平均加工时间减少，设备利用率提升；而且更大尺寸的硅片使得边缘芯片减少，提升成品率。 2.按拉晶工艺分： CZ直拉法，占85%，一般用于CMOS、Memory等大部分工艺器件 FZ区熔法，一般用于RF、IGBT等 3、按使用用途分：抛光片PolishWafer 外延片EpitaxialWafer:外延生长形成的具有单晶薄膜的衬底晶片通常被称为外延片。通过气相外延沉积的方法在衬底上进行长晶，与最下面的衬底结晶面整齐排列进行生长。外延硅晶片广泛使用在二极管，IGBT功率器件,低功耗数字与模拟集成电路及移动计算通讯芯片等。退火片ArgonAnneal:抛光片用氢气或氩气通过加热处理后，更进一步提高表面的结晶品质。广泛用在功率器件,数字与模拟集成电路及存储器等芯片。绝缘体上硅(SOI)Silicon-On-InsulatorWafer:是一种三明治结构，最上面是顶层硅，中间是掩埋氧化层（BOX），下方是硅衬底。制备SOI材料的技术主要有注氧隔离（SIMOX）、键合减薄（BESOI）和智能剥离（Smart-Cut）等，当前最主流的技术是智能剥离。SOI的优势在于可以通过氧化层实现高电绝缘性，这将大大减少硅片的寄生电容以及漏电现象。在28nm以下先进制程中，FD-SOI（全耗尽SOI）具有明显的低功耗，防辐射，耐高温的性能优势，同时采用SOI方案可以大大减少工序，降低成本。测试片Test Wafer：mechnical wafer、particle wafer、control wafer、superflat wafer、special wafer（如oxide/nitridewafer）等。主要用于实验及检查等用途。在制造设备投入使用初期，也被大量使用以提高设备稳定性。由于使用目的不同于通常使用的晶圆片产品，因此TestWafer中再生晶片被普遍使用。控片Monitor Wafer:主要用于在正式的集成电路制造之前对于各道制程实施必要的调整。除此之外也可用于监测，与晶圆产品一同在各工程流动。挡片Dummy Wafer:又称假片，调试级硅片主要用于半导体设备和工艺调试，达到一定的工艺要求。其中挡片和控片一般是由晶棒两侧品质较差处所切割出来，用于调试机台、监控良率。随着晶圆厂制程的推进，基于精度要求及良率的考量，需要在生产过程中增加监控频率。65nm制程每投10片正片，需要加6片挡控片，而28nm及以下制程，每10片正片需要加15-20片挡控片。挡控片的用量巨大，为了避免浪费，晶圆厂往往会回收用过的挡片，经研磨抛光，重复使用，但挡片的循环次数有限，一旦超过门限值，则只能报废处理或当做光伏硅片使用。而控片则需具体情况具体对待，用在某些特殊制程的控片无法回收使用，那些可以回收重复利用的挡控片又被称为可再生硅片（reclaimedwafer）。市场格局全球：在全球半导体材料产业链，国外巨头占据了主要的市场份额。前五大厂商分别为日本信越半导体（份额27%）、日本胜高科技（26%）、台湾环球晶圆（17%）、德国Silitronic（11%）、韩国LG（7%），市场占有率达到92%。其中，仅两家日本企业所占的全球市场份额就超过50%。在12寸硅片市场中，前五大厂商更占据将近98%的市场份额。国内：目前我国12英寸硅片主要依赖进口，（曾有段时间据传SMIC中芯国际的12寸线的wafer缺货，日本厂商优先供应别家）；8英寸硅片的自给率也不高，目前在10%左右。根据芯思想统计，截止2017年11月，我国12寸硅片需求量为45万片（包括三星西安、SK海力士无锡、英特尔大连、联芯厦门），随着晶合集成、台积电南京和格芯成都的陆续投产，加上紫光南京、长鑫合肥、晋华集成三大存储芯片厂的建成，预估到2020年我国12寸硅片月需求量为80-100万片。抛开外资晶圆厂（三星西安、SK海力士无锡、英特尔大连、联芯厦门、台积电南京、格芯成都）的产能，国内的月需求量约为40-50万片。目前我国12英寸硅片主要依赖进口，但规划中的月产能已经达到120万片，后续如均能顺利量产，可基本满足国内需求。（前提是能量产、满产） 8寸硅片方面，据芯思想统计，截止至2016年底，我国具备8英寸硅片和外延片生产能力的公司合计月产能为23.3万片/月，实际产能利用率不足50%，2016年全年我国仅仅产出120万片8寸硅片，只满足国内的10%的需求。从目前已经公布的产能来看，8寸硅片月产能已经达到140万片，合计超过160万片，远远超过我国8寸硅晶圆的月需求80万片的规模。而SOI硅片则由于它的特殊性，所以其供应商和主流的硅片厂商不同。目前国际上最大的SOI供应商为法国Soitec，上海硅产业投资有限公司已收购其14.5%股份。其他供应商为日本信越，Sumco等。而国内的供应商主要为上海新傲，也是上海硅产业集团的子公司。产能方面，目前Soitec位于法国Bernin2工厂以及新加坡PasirRis工厂主要生产300mm晶圆，未来最大产能将达200万片，而Bernin1和新傲科技的200mm晶圆厂最大产能将达100万片。国内主要硅片生产企业公司名称产品规格（英寸）公司简介有研半导体 4/5/6/8（少量）/12（少量）系中央企业北京有色金属研究总院全资子公司，主要从事硅和其他电材料的研究、开发、生产与经营。上海新傲科技 4/5/6/8（少量）一家致力于高端硅基材料研发与生产的高新技术企业，是中国领先的SOI材料生产基地。浙江金瑞泓科技 4/5/6/8（少量）公司是中国大陆唯一具有硅单晶锭、硅研磨片、硅抛光片、硅外延片、芯片制造的完整产业链的半导体企业，8英寸硅片月产12万片。天津中环半导体 4/5/6/8（少量）是一家致力于半导体节能产业和新能源产业，拥有独特的半导体材料-节能型半导体器件和新能源材料-高效光伏电站双产业链。南京国盛电子 4/5/6/8（少量）前身是信息产业部电子第五十五研究所电子材料产品部,专业从事半导体硅外延材料的研发及批量生产。河北普兴电子 4/5/6/8（少量）致力于高性能硅基材料的外延研发和生产，是中国规模最大的硅外延材料生产基地。超硅半导体 6/8（少量）/12（少量）超硅目前拥有上海超硅半导体有限公司和重庆超硅半导体有限公司，致力于为全球集成电路制造商提供高品质的大尺寸硅片。上海新昇半导体 12（少量）是中国内地唯一一家，规模最大的12寸大硅片生产企业，预计未来最终将形成300mm硅片60万片/月的产能。资料来源：各公司官网，申万宏源研究上海新昇（上海新阳（300236.SZ）参股 24.36%）的大硅片项目目前已经实现了挡片的批量供货，正片也有小批量样片实现销售，目前产能 4-5 万片/月，预计 2018 年产能可达 10 万片/月；中环股份（002129.SZ）于 2017 年 10 月 13 日和无锡市签署《战略合作协议》，共同在宜兴市建设集成电路用大硅片生产与制造项目。项目总投资约 30 亿美元，一期投资约 15 亿美元；重庆超硅的 12 寸硅片开发进展也较为顺利。同时硅产业集团旗下的上海新傲的 SOI 产线是中国硅片产业的一大亮点表：中资企业积极布局大尺寸硅片企业项目硅片尺寸（英寸）规划产能项目进展上海新晟 12英寸大硅片项目一期 12 15万片/月 2018年中达产 12英寸大硅片项目二期 12 扩充至60万片/月 2021年满产郑州合晶 8英寸硅片项目 8 20万片/月 2018年Q2量产5万片/月，2019年Q2满产 12英寸硅片项目 12 20万片/月 2017年底开工重庆超硅 8英寸、12英寸硅片项目一期 8、12 15万片/月 2016年12月达产 8英寸、13英寸硅片项目二期 8、12 扩充至30万片/月 2018年12月达产 8英寸、14英寸硅片项目三期 8、12 扩充至50万片/月 2020年12月达产宁夏银和大尺寸半导体硅项目一期 8 15万片/月 2017年7月达产大尺寸半导体硅项目二期 8、12 8英寸：35万片/月 12英寸：20万片/月预计2018年投产浙江金瑞泓半导体硅片项目一期 8 10万片/月 2017年底达产半导体硅片项目二、三期 8、12 扩充至8英寸：40万片/月 12英寸：10万片/月预计2019年达产北京芯动能西安高新区硅片生产基地项目 12 未知未知中环晶盛天津8英寸半导体抛光片项目 8 30万片/月 2018年10月达产天津12英寸抛光片试验线 12 2万片/月 2018年底达产大直径抛光片产业化项目（8英寸） 8 75万片/月 2022年达产大直径抛光片产业化项目（12英寸） 12 60万片/月 2022年达产资料来源：百家号，中时电子报，elecfans，重庆市经济和信息化委员会，公司公告，申万宏源研究供需结构 12寸 2017 年-2022 年，12 寸硅片需求的复合增长率为 4.3%。其中 3D NAND 对硅片需求的复合增长率为16.76%，成为未来 3 年里 12 寸硅片需求增长的主要驱动力。当前前五大厂商各家硅片厂均相对保守，更倾向于控制产能扩张，推动涨价，抬升利润水平。 8 寸汽车电子主导 8 寸硅片需求，晶圆厂通过涨价转移成本压力。 2016年起，8 寸线的驱动力主要在指纹识别，进入 2018 年，随着汽车电子， IOT 等应用的兴起，8 寸线的供需关系依旧偏紧从最直接的，硅片的直接客户就是芯片代工厂，除了现有需求，国内新增的代工厂产能如下，这些都是新增的需求：表：国内在建及拟建晶圆厂汇总状态晶圆尺寸序号公司设计产能（千片/月）在建 12英寸 1 德科码 20 2 华力微 40 3 晋华集成 60 4 晶合集成 40 5 武汉新芯 200 6 中芯国际 40 7 中芯国际 35 8 中芯国际 35 9 中芯国际 70 10 台积电 20 11 格芯 20 12 合肥晶合 40 8英寸 1 德科码 40 2 中芯国际 150 3 士兰集成电路 20 拟建 12英寸 1 安积电 2 德科码 40 3 合肥长鑫 125 4 万代半导体 20 5 中芯国际 6 中芯国际 7 中芯国际 8 紫光 40 9 紫光 100 10 格芯 65 资料来源：OFweek，中国报告网，EEPW，上海证券网，申万宏源研究据估计，目前全球8寸与12寸半导体硅晶圆每月出货量大约各在520万片至530万片之间，但每月的潜在需求量可能达600万片以上。供需差的原因（来自海通证券）： 1）全球晶圆代工大厂台积电、三星电子、英特尔进入高端制程工艺竞赛，20nm以下的先进工艺将在整个晶圆代工中的比例越来越高，先进的工艺对高质量大硅片的需求越来越大； 2）三星、SK海力士、英特尔／美光、东芝等全力投入3DNAND扩产，3DNAND的投资热潮将刺激300mm大硅片的需求； 3）尽管智能手机的增速放缓，但是手机创新不断，对高端300mm硅片需求仍将快速增长。同时工业与汽车半导体、CIS、物联网等IC晶片开始快速增长，这为8寸和12寸硅片带来新的增量； 4）大陆半导体厂商大举扩产，更是不可轻忽的势力，2016至2017年间，全球确定新建的晶圆厂19座，其中中国大陆就占了10座。 8/12寸市场补充： 12寸市场：除了供需原因导致的12寸硅片市场紧缺以为，12寸硅片市场被看重的原因还有: 芯片的成本与硅片面积有直接关系，在面积大的硅片上，一次能够蚀刻出更多的芯片，并且芯片撞上硅片缺陷的概率变低，提高芯片的良品率。因此，半导体产业一直在追求面积更大的芯片。根据计算公式：每个硅片生产的芯片数=（硅片的面积/芯片的面积）-（硅片的周长/（2*芯片面积）的开方数），12寸硅片一次能制造的芯片数约为8寸硅片的2.5倍。根据SEMI，各尺寸硅片成为主流尺寸的时间点分别为：1986年4英寸，1992年6英寸，1997年8 英寸，2005年12英寸。目前，12寸硅片已成为业界主流，占所有硅片需求的60%以上，而6/8 寸硅片的需求比例被进一步压缩。由于制造设备更换和良品率等问题，18寸硅片的研制虽然已投入数年，但成本高、回报低的问题一直没有得到很好的解决，陷入停滞，预计未来数年12寸硅片仍将是市场主流。大 8寸市场： 12寸硅片尽管有种种优点，但是其需要大批量的生产才能降低其芯片的单体成本。但是8寸晶圆制造厂相对于12寸厂：（1）拥有特种晶圆工艺；（2）完全或大部分折旧的固定资产的固定成本较低；（3）光罩及设计服务的相应成本较低；（4）达到成本效益生产量要求较低，等方面的优势。同时，2010~2016年约有25座6寸晶圆厂关闭，相应6寸晶圆产能会转移至8寸线晶圆厂。因此8寸晶圆和12寸晶圆能够实现优势互补、长期共存。产能缺口投资小结 1、硅片生产企业：就看谁的硅片质量能达标能尽快量产尽快跟上产能，享受当下硅片剪刀差的红利，内资企业里优先的上海新昇、中环股份、重庆超硅概率大。唯一需要担心的就是国内外企业产能都开出来之后，供需结构如果逆转，那就比较尴尬了。不过当下，远的不说，近一两年内，谁先量产谁先受益。 2、硅片设备企业：设备这块没在本文里写，以前的文章里提了很多。硅片生产企业里的投资，6成要投入设备，国内能提供设备的屈指可数，值得重点关注，就希望国内企业能善待国内设备企业，共同成长。注：文章数据表格等等参考引用了申万宏源、招商证券、方正证券、海通证券等卖方报告并进行了整理，在此一并感谢。再注：写的很乱，排版也很乱

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wafer 在英語-中文（繁體）詞典中的翻譯

wafernoun [ C ] uk

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/ˈweɪ.fər/ us

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/ˈweɪ.fɚ/

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a very thin, dry biscuit that is often sweet

薄酥餅;威化餅乾

religion

specialized a very thin, round piece of dry bread that the priest gives to people to eat during Holy Communion

（基督教徒在聖餐儀式上食用的）聖餅

Indian English a very thin, often round piece of fried potato or other vegetable, sometimes with a flavour added

薄圓炸土豆餅;薄圓炸蔬菜餅

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wafers是什么意思_wafers的翻译_音标_读音_用法_例句_爱词霸在线词典

rs是什么意思_wafers的翻译_音标_读音_用法_例句_爱词霸在线词典首页翻译背单词写作校对词霸下载用户反馈专栏平台登录wafers是什么意思_wafers用英语怎么说_wafers的翻译_wafers翻译成_wafers的中文意思_wafers怎么读,wafers的读音,wafers的用法,wafers的例句翻译人工翻译试试人工翻译翻译全文简明柯林斯牛津wafers英 ['wefɚ]释义n.封信条( wafer的名词复数 ); 薄脆饼; <电>薄片; 圣饼点击人工翻译，了解更多人工释义实用场景例句全部Remove the wafers with a spoon and transfer them to a plate.用勺子抄起薄饼，把它们转盛到盘子里。柯林斯例句Large diameter wafers are feasible and 200 - mm wafers have been produced.大直径片子已不难制造,200mm的片子也已产生了.辞典例句All organic and metallic residues on the wafers must be removed.片子上所有的有机和金属残留物均必须清除.辞典例句Personnel must wear proper clothing to protect the wafers.工作人员必须穿适当的服装以保护硅片.辞典例句The dust produced during slicing weighs almost as much as the wafers.在切割时所产生的碎屑几乎和薄片一样重.辞典例句Historically, wafers were waxed onto a metal plate.过去片子是用石蜡固定到金属板上.辞典例句The processing characteristics and some material properties of silicon wafers depend on the orientation.硅片的工艺性质与某些材料特性均与晶向有关.辞典例句The reactors for this type of deposition are easily scaled to accommodate 125 - or 150 - mm wafers .这种淀积反应器很容易达到适应125或 150mm 的基片.辞典例句Laser making of wafers for identification purpose will also become a new attribute.为了定位,片子上的激光标记也将成为新的标志.辞典例句No food that I could dream of seemed half so utterly delicious as vanilla wafers.我所梦想的任何食物都不如香草薄饼那么可口有味.辞典例句Place the Copper side face down on your wafers.将铜盘面朝下置放在晶片上.互联网Bonding Interface - The area where the bonding of two wafers occurs.绑定面 - 两个晶圆片结合的接触区.互联网Food Quality - In the beginning, you can only feed your fish wafers.鱼食质量升级:游戏开始, 你只能够给鱼喂食薄饼碎屑.互联网A container in which wafers for the Eucharist are kept.圣饼盒装圣餐用的饼干的容器.互联网All right . We'll have some cheese wafers and caviar.我们点一些干酪薄脆饼和鱼子酱.互联网收起实用场景例句释义实用场

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The wafer - Waferfabrication - Semiconductor Technology from A to Z - Halbleiter.org

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Wafer Fabrication:

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Wafer separation and surface refinement Historical development of the wafer size Why are silicon wafers round?

1. Wafer separation and surface refinement

At first the single crystal is turned to a desired diameter and then bedight with one or two flats. The larger, first flat allows an precise alignment of the wafer during manufacturing. The second flat is used to detect the type of the wafer (crystal orientation, p-/n-type doped), but is not always used. Wafers with a diameter of 200 mm or above use a notch instead. This tiny notches on the edge of the disk also provide an alignment of the wafer, but take up much less costly wafer surface.

Sawing

With an annular saw, whose cutting edge is filled with diamond splinters, the single crystal is sawn into thin discs = wafer. The saw provides a high accuracy during sawing without bumps. Up to 20 % of the crystal rod is lost due to the width of the saw blade. However, nowadays more often wire saws are used, in which multiple wafers can be cut at once from the staff. Therefore a long wire, which is wetted with a suspension of silicon carbide grains and a carrier (glycol or oil), is lead through rotating rollers. The silicon crystal is drained into the wire grid and thus cut into single wafers. The wire moves in counterstep with about 10 m/s and has a typically thickness of 0.1-0.2 mm.

Annular saw and wire saw

After sawing, the slices have a rough surface, and due to mechanical stress damages in the crystal lattice. For finishing the surface, the wafers pass several process steps.

Lapping

Using granular abrasives (e.g. aluminum) 50 microns (0.05 mm) of the wafer surface are removed on a rotating steel disc. The grain size is reduced in stages, but the surface is re-injured due to the mechanical treatment. The flatness after lapping is about 2 microns.

Beveling of the edge

In subsequent processes, the discs must have no sharp edges, as deposited layers may flake off otherwise. Therfore the bevel of the wafers are rounded with a diamond cutter.

Etching

In an additional wet etch process, with a mixture of hydrofluoric, acetic, and nitric acid, 50 microns are removed. Because this is a chemical process, the surface is not damaged. Crystal defects are permanently resolved.

Polishing

This is the final step of surface refinement. At the end of the polishing step, the wafers do not have a bump of more than 3 nm (0.000003 mm). The wafers are treated with a mixture of sodium hydroxide NaOH, water, and silicon oxide grains. The oxide removes additional 5 microns from the surface, the hydroxide removes machining marks caused by the oxide grain.

2. Historical development of the wafer size

The manufacture of integrated circuits on silicon wafers started in the mid 1960s on wafers with a diameter of 25 mm. Nowadays, in modern semiconductor manufacturing wafers with a diameter of 150-300 mm are used. By 2012 the mass production of microchips on wafers with a diameter of 450 mm is expected; prototypes have already been produced for research purposes. The wafer surface is then increased by more than 300-fold of the tiny 1-inch wafer 50 years ago, whereas the disk diameter was only increased by a factor of 18.

With larger wafers, the throughput rate increases significantly in the manufacture of microchips, whereby the cost is reduced accordingly in the production. Thus, with identical structure sizese more than twice as many chips can be produced on a 300 mm wafer as on a 200 mm wafer. In addition, with increasing diameter the wafer's edge is less curved and thus the cut-off minimized (since chips are off rectangular shape).

Typical data of wafers:

Type [mm]

Diameter [mm]

Thickness [µm]

Main flat [mm]

Bow [µm]

150

150 ± 0,5

~700

55 - 60

200

200 ± 0,5

~800

Notch

300

300 ± 0,5

~900

Notch

Different sizes of wafers: 25, 38, 51, 75, 100, 125, 150, 200, 300, 450 [mm] (scaled)

3. Why are silicon wafers round?

Wafers are fabricated in a round shape although the final microchips are rectangular. Therefore there is always some blend on the wafer - some area where no entire chips can be placed and which has to be discarded at the end of the semiconductor manufacturing.

After the description of the two manufacturing processes - the Czochralski process and the Float-zone process - this procedure is understandable.

A silicon wafer for microchip fabrication needs to be in single crystalline shape. This is only possible by using the two mentioned techniques which deliver a round wafer.

Even if it is possible to cut the round single crystal into rectangular shape afterwards (e. g. by sawing) the round wafers have several advantages over an angular shape.

Straightening the round silicon causes additional stress to the crystal, leading to defects and dislocation and finally a worse quality of the silicon

Round wafers are more stable, angular wafers could hardly be transported and processed without damage

A homogen processing during microchip manufacturing with radially symmetrical processes (CPM, etching, spin on) is much easier

Also on angular wafers a small area on the extreme edge would have to be discarded since the processing can't be done to the outermost edge. The wafers need to be clamped during transport and layers would spalling off if reaching to the edge

With increasing wafer surface the blend can also be reduced.

Rectangular wafers, however, can be found in solar cell manufacturing. In general polycrystaline wafers are used which can be poured in a rectangular form. The manufacturing is relatively easy compared to microchip fabrication, so that angular wafers can be used; the edges can also be chamfered.

Next: Doping techniques

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The Importance of Wafer Edge in Wafer Bonding Technologies and Related Wafer Edge Engineering Methods - IOPscience

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ECS Journal of Solid State Science and Technology

The Electrochemical Society (ECS) was founded in 1902 to advance the theory and practice at the forefront of electrochemical and solid state science and technology, and allied subjects. Find out more about ECS publications

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The Importance of Wafer Edge in Wafer Bonding Technologies and Related Wafer Edge Engineering Methods

Roy Knechtel4,1, Uwe Schwarz2, Sophia Dempwolf2, Holger Klingner2, Andy Nevin2, Gunnar Lindemann2 and Marc Schikowski3

Published 30 July 2021 •

ECS Journal of Solid State Science and Technology,

Volume 10,

Number 7

Focus Issue on Semiconductor Wafer Bonding: Science, Technology, and Applications

Citation Roy Knechtel et al 2021 ECS J. Solid State Sci. Technol. 10 074008

DOI 10.1149/2162-8777/ac0f14

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Author e-mailsr.knechtel@hs-sm.de

Author affiliations1

Schmalkalden University of Applied Sciences Autonomous Intelligent Sensors, Chair of the Carl-Zeiss-Foundation, Schmalkalden 98574, Germany

X-FAB MEMS Foundry GmbH, D-99097 Erfurt, Haarbergstrasse 67, Germany

X-FAB MEMS Foundry Itzehoe GmbH, Fraunhoferstraße 1, 25524 Itzehoe, Germany

Author notes4 Electrochemical Society Member.

ORCID iDsRoy Knechtel https://orcid.org/0000-0002-2272-6924

Dates

Received 2 May 2021

Revised 18 June 2021

Published 30 July 2021

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2162-8777/10/7/074008

Abstract

Wafer bonding is an important process step in microsystem technologies for processing engineered substrates and for capping. Usually, the work and literature are focused on the bonding of the main wafer area. However, in recent years MEMS technologies have become more complex, with more process steps after wafer bonding. Accordingly, the wafer edge is becoming more and more important, and must be engineered. Methods for realizing this are discussed in this paper.

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Semiconductor Wafer Bonding is a key process step for many technologies such as engineered substrates (SOI and cavity SOI Wafers), MEMS (sensors, microfluidics), 3D integration (device stacking) and wafer thinning (temporary wafer bonding). Almost all publications in the field of wafer bonding are concerned with how bonding is working and can be performed at the actual wafer area. It is also well known that any disturbances on the wafer surface, such as particles, scratches, areas with increased surface roughness, or surface steps from the wafer processing act in most of the wafer bonding technologies as points of discontinuity with negative influence on the bonding behavior (generation of voids, non-hermeticity, reduced bonding strength). Due to the general geometry of the wafers and their defined sizes, they have an edge. This wafer edge has special properties and also acts as an area of discontinuities. Even in well-established wafer bonding techniques, which allow close to perfect bonding of the wafer area, there are smaller or wider unbonded areas at the wafer edge. In particular, in industrial production processes, these unbonded areas are often the cause of process problems in the process steps after wafer bonding. For example, wet chemicals can be trapped in these kinds of unbonded areas, and become released later into other tools, parts of the poorly bonded wafer edge can flake off, and in the grinding process wafers can break due to missing mechanical support at unbonded edge areas. The reasons for these unbonded areas can originate in different process areas, such as the raw wafer manufacturing (here the wafer edge is initially defined), in the wafer processing before bonding (for every process step the wafer edge is a zone of discontinuities with special effects and inhomogeneities), in the bonding process (here the bonding needs to be formed up to the very edge of the wafer) and in the process steps after the wafer bonding (bonded wafer edges can be easily damaged). There is some literature available about the topic wafer edge engineering for wafer bonding, but either as general introduction

or as special solution for special applications like 3D Integration

or in relation to special bonding methods

(surface activated bonding). In this paper the influence of wafer edge effects on very different wafer bonding technologies, such as direct, anodic and glass frit bonding, is discussed, and various countermeasures and improvements are described in detail.Wafer Edge Aspects at Wafer Bonding for Engineered SubstratesSemiconductor wafer bonding is used to process special engineered substrates, such as cavity SOI-Wafers, to allow the advantageous production of absolute pressure sensors. Here, one wafer, which later becomes the pressure sensor membrane by grinding and polishing, has to be bonded to a carrier wafer containing etched cavities. Both the processing of the cavity SOI wafers and the processing of the actual pressure sensors are illustrated in Fig. 1, with further details given in Ref. 4.

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Figure 1. Principle process flow for discrete and CMOS integrated absolute pressure sensors based on cavity SOI wafers as engineered substrates.Download figure: Standard image

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For discrete pressure sensors, the use of bulk wafers is sufficient for the membrane, but due to the edge roll-off, which gives a very slight transition from the actual wafer edge to the actual wafer area, some unbonded areas occur at the wafer edge, which disturb the subsequent processing (chemical trapping, flaking). For CMOS integrated pressure sensors, wafers with an epitaxially grown silicon layer must be used as membrane wafers to ensure a very high silicon quality necessary to ensure the required gate oxide quality of the CMOS transistors. These epi wafers often have a so-called epi crown, a ridge at the wafer edge resulting from the growth of the epitaxial layer. In the epi growing process, the wafer edge acts as a discontinuity, which results, depending on the epi-reactor type, in a locally-significant increased epi deposition rate, which finally forms the ridge. Depending on its form, this epi crown, over a wide area but not all around the wafer edge, prevents both wafers from coming into the close contact required to form the direct bond. This results in a poor bonding yield, and the wafers often cannot be processed further on production tools. As already mentioned, the epi crown is not present all around the wafer edge, which results in non-uniform bonding. Areas of the wafer edge where no epi crown is present are bonded well, while in other areas of the edge, the epi crown is so high that the resulting unbonded area can be up to several mm wide, which is critical for further processing steps. The behavior of the epi crown in direct wafer bonding processes is illustrated schematically in Fig. 2, and in Fig. 3 by an IR transmission image with measurement values.

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Figure 2. Unbonded areas at bonding wafers with epitaxial layers related to the epi crown phenomena.Download figure: Standard image

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Figure 3. Infrared image of unbonded wafer edge areas and epi crown investigations with edge shape and epi crown height if present.Download figure: Standard image

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Since the bonding vacuum should be sealed in the pressure sensor reference cavities, the bonding problems related to the epi ridge crown can be even more critical. Because the bond front can continue to propagate after removing the wafer from the bonding chamber, there is a risk of forming well-bonded cavities which are filled with air. This will result in non-functional pressure sensor chips, and, even more importantly, a high risk during the wafer processing from fracturing of membranes in high-temperature processes, when the sealed air expands.To achieve bonding up to the wafer edge, different measures are possible. Firstly, special unsymmetrical edge geometries with reduced edge roll off, can be used for the bulk wafers.

These types of wafer with an unsymmetrical wafer edge are now commercially available, and are realized in raw wafer processing by tilting the edge grinding tool relative to the wafer surface. As a result, there is only a very small rounded edge zone on the front side, but a larger one on the backside already from the wafer edge grinding (Fig. 4), which also helps to minimize further edge rounding in the subsequent polishing of the wafer surface, the final part of the raw wafer process. With this approach, the flat, undisturbed area of the wafer surface is extended quite close to actual wafer edge, which enables the semiconductor direct bonding to occur very close to the physical wafer edge, thus reducing the unbonded edge areas as shown in Fig. 5 in cross section analysis and as reduced chipping of unboned membrane layers after the grinding process in Fig. 6. Wafers with this kind of unsymmetrical edge bevel profile were initially developed to improve the back grinding process, in order to prevent very sharp and fragile wafer edges when thinning wafers down to 100 μm or below,

and are now commercially available also for wafer bonding applications.

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Figure 4. Drawing unsymmetric edge geometry as an example and as used for the following investigations (values in μm).Download figure: Standard image

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Figure 5. Cross section of different wafer edge profiles after bonding (left unsymmetrical special wafer edge, right standard symmetric wafer edge.Download figure: Standard image

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Figure 6. Reduced membrane wafer chipping at wafer edge at unsymmetric wafer edge configuration (left) compared to stand wafer edge configuration(right)—top view on bonded and grinded wafer stack using optical microscope (scales in μm).Download figure: Standard image

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As another way to engineer the bonded wafer edge in advance, the wafer edge can be lowered in a defined way before the direct bonding, by a masking and silicon etching processes, to produce a very clean, well-bonded wafer edge after grinding and polishing of the membrane wafer.

For the etching process, wet chemical etching, such as KOH etching (as shown for example in Fig. 7), as well as plasma-based dry etching, such as DRIE-processes, can be used. It is important here not to damage or roughen the actual wafer bonding surface when etching the wafer. In practice, this means that the mask material has to be thick and dense enough to keep the etch medium away from the bond surface, and that the mask material must be stripped off gently without effecting the bond surface. Here, wet strip processes for resist or hard masks are recommended. This preparation process can be used for standard bulk and for epi wafers to ensure a very well-defined, recessed edge for the membrane or device wafer layer after bonding and thinning. This lowers the remainders of the epi crown below the bonding surface level (Fig. 8) if etching is deep enough, thus allowing a very good bonding yield when bonding epi-wafers. It can be also used for bulk wafers to obtain a very well-defined wafer edge, since the bonding of the edge roll off zone of the wafers is actively excluded by recessing the wafer edge area. In Fig. 9 bonding issues at not conditioned wafer edges (here with epi crowns) are compared to the bonding of wafer with lowered wafer edge. It is clearly to see that the unbonded edge zones is reduced by the etched area and by this well-defined and controlled. The cross section in that figures confirms in addition the very well defined wafer edge construction without any unbonded areas.

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Figure 7. Principle and results of wafer edge zone lowering by KOH etching to improve wafer bonding behaviour at wafer edge.Download figure: Standard image

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Figure 8. Profiler measurement at etched edge zone of an epi wafer, showing that an etching depth of 20 μm is required to lower the remaining epi crown profile below the bonding surface of the wafer (zero level in this diagram).Download figure: Standard image

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Figure 9. Infrared images of bonded wafers; left uncontrolled unbonded zones when bonding epi wafers with epi crowns, bonding of epi wafers with lower epi crowns resulting small very defined unbonded wafer edge area and cross section images after membrane/device wafer grinding and polishing, to show the actual edge of the bonded construction.Download figure: Standard image

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Figure 10 summarizes the general issue of the unbonded wafer edge when performing semiconductor direct wafer bonding using standard wafers, and compares the described countermeasures of wafer edge engineering prior to bonding.

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Figure 10. Wafer edge engineering before semiconductor direct bonding for absolut pressure sensors.Download figure: Standard image

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Alternatively to engineering of the wafer-edge before wafer bonding, the edge of bonded wafer stacks can also be trimmed. Using special grinding tools and grinding wheels, the edge of the bonded, thinned device or membrane wafer of the engineered substrate can be removed

(Fig. 11). Here, while a very well-defined edge can be realized, special tools are needed, and the grinding causes risks to the wafer: loose parts of the device or membrane wafer can flake off and damage the wafer surface, and, since the new wafer edge is machined, it contains micro-damage, which can lead to breakage of these expensive substrates, or to problematic processing interactions such as adhesion or wetting issues. For these reasons, and since the required specialized edge grinding tools are often not available, the option of edge engineering before wafer bonding should be used for special substrates such as cavity SOI wafers.

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Figure 11. Principle of wafer edge grinding after bonding and thinning—removal of the loose, unbonded edge part of the device or membrane wafer layer.Download figure: Standard image

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Wafer Edge Aspects at Wafer Cap Wafer BondingIn MEMS wafer processing, the capping of fragile mechanical structures using wafer bonding is a very important process step. As well as mechanical protection it often also provides a hermetic sealing and a defined atmosphere which is required for a defined functionality of the sealed elements. For example, gyroscopes require vacuum sealing to attain good Q-Factors of their actuation part, which is the requirement for sensing based on the Coriolis force. Acceleration sensors, in contrast, need some damping for optimum functionality. For these types of sensor, glass frit bonding is widely used, and some of the specific edge effects of this process will be discussed later. But before coming to the specific aspects of this wafer bond technology, some general points of cap wafer bonding (Fig. 12) should be discussed.

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Figure 12. Examples of bonded cap wafer on system wafer with discrete inertial sensors (gyroscopes)—left detail photographs of unbonded and bonded wafers, right schematic cross section.Download figure: Standard image

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General aspects of cap wafer bondingThe most specific aspect of cap wafer bonding is that wafers are bonded which have gone through a long and complex wafer process. Usually one wafer contains the structures which require capping as described above. This wafer is termed the "system wafer" in this paper. It can be a wafer containing MEMS-Sensors, microfluidic structures, or optical sensing elements, all either as discrete elements or as CMOS integrated systems. The cap wafer is usually a less complex construction. Typically, it has some cavities on the bonding side in which the required atmosphere for the sensor elements is defined by bonding, holes to reach the wire bond pads after the bonding process, and optionally, counter electrodes and additional wire bond pads. However, cap wafers can be even more complex, and can have through-silicon vias or even ASICs for the signal conditioning. Whatever the actual configuration, the wafers are heavily processed, both going through typically 20 to 40 lithography layers. As a result of this, the wafer edge is very undefined. In every lithography layer a so-called edge bead removal is performed, which is a step to remove surplus resist from the wafer edge, which would contaminate subsequent process tools. This means that there is no resist at a zone of 1 to 3 mm inside the actual wafer edge, so that all deposited layers are etched away, but in a poorly controlled way. On one hand, the edge bead removal is not well defined and not aligned in all the lithography layers, while on the other hand, the etching tools also have wafer edge effects. Figure 13 illustrates what this kind of edge of a fully-processed MEMS-CMOS wafer looks like.

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Figure 13. Detailed investigation of the edge of a CMOS processes system wafer.Download figure: Standard image

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It is quite clear to see that the wafer edge area is undefined after processing of several lithography layers. At the outer edge, the silicon is undefinedly etched and roughened, there are also residues from various process layers, and in an adjacent zone there are undefined partial chip structures, which arise from stepper exposure and unaligned edge bead removal in the different process layers. It is quite obvious that wafer bonding technologies which usually require flat, clean and defined surfaces cannot work well here. Even bonding processes such as glass frit bonding, which are quite tolerant regarding surface quality do not work well on this kind of wafer edge, since either the glass frit is unable to come into contact with the surface—often in MEMS Technologies with front side release processes, the silicon surface at the wafer edge is also etched and lowered by this—or the wetting behavior is poor, so that a bond cannot be formed. It is also clear that on this kind of wafer edge, the deposition and structuring of bonding layers such as metals for solder thermocompression or eutectic bonding cannot work. Protecting and defining the wafer edge in every process layer is theoretically possible, but does not work in practice—the effort to realize this in a 20 to 40 layer process is extremely high. The edge bead removal is a must in industrial processes, etching tools with edge protection rings have limited availability, and wet processes attack the wafer edge anyway. Therefore, active edge engineering before the bonding of cap wafers is seldom possible nor sensible. However, since the cap wafer bonding is usually done at the end of the wafer process, edge trimming is a good option for producing a new, defined, and well-bonded wafer edge. This kind of fixed, and solid edge of the cap wafer bonded wafer stack is very important, for 3 main reasons (see also Fig. 14).

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Figure 14. Description of risks in grinding (left) and dicing (right) related to unbonded edges in cap wafer bonding applications.Download figure: Standard image

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The back grinding of the wafers: bonded wafers are very stable, but thick, so back grinding to get thinner wafer chip constructions for fitting into modern packages is often done. At grinding there is a high pressure on the wafers, so that cracks can occur and grow at unsupported wafer edges, causing the complete wafer to break and be lost.At dicing, unbonded parts at the wafer edge can fly off and damage the dicing blade, which can even break. This can be a sufficient enough disturbance of the dicing process to make it impossible in industrial environment for wafer stacks with poor bonded edges.Not in very case can the cap wafer be completely finished before the bonding is performed. Contacts from the cap to the system wafer can be better made after the bonding (through-silicon vias—TSV), or sensitive layers, which might be damaged in the bonding process must be deposited and structured after the bonding step. Here, as mentioned, it is important to have a bonded and sealed edge to prevent trapping and uncontrolled release of process chemicals.A very suitable technique for edge trimming of bonded, capped wafers is the circle cut method. Here, in a classical blade dicing process, the original wafer edge is removed through the full thickness of the bonded wafer stack, or just through the cap wafer. The circle cut is normally an option with state-of-the-art dicing tools,

and the width of the removed edge ring can be adjusted to cover the entire unbonded area. For the full-thickness circle cut, it is important, that the cut is done through the well-bonded zone, so that the complete unbonded wafer edge area is removed. A drawback of this method is that the diameter of the wafer is reduced by several millimeters, and, although for some subsequent wafer processing, such as dicing or grinding, this is not normally an issue, if complex handling is needed, such as for wafer probing or lithography, the new wafer diameter no longer fulfills the Semi Standard M1-1107,

which can be a serious problem. In extreme cases, if the unbonded area at the wafer edge is too high and the removed ring is too broad, the wafer diameter can be reduced so much that the wafers no longer fit into standard carriers, and special magazines or boxes must be used, which at best requires a larger effort, or can make wafer handling impossible. In this case, a partial circle cut is an option, where the dicing blade cuts through only one of the wafers, often the cap wafer, so that only the edge of this wafer is removed, while the other wafer remains intact. Here, the cutting must be carried out in the unbonded area, so that the one loose edge can be easily removed. The consequence of this approach is that a small amount of unbonded area can remain, because the alignment of the dicing blade to the edge and the unbonded area (often it has some irregularities in shape) has limited precision. It must also be taken into account, that the blade damages at least a small part of the second wafer, which can also result in wafer breakages. Figure 15 illustrates both edge removing principles by circle cutting. The full circle cut, which removes both wafer edges, gives the cleanest result, but the partial wafer cut of just one wafer retains the standard diameter of the wafer, which is typically used for the handling. Both methods have relevance for different applications.

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Figure 15. Circle cut principle and usage at bonded wafer stacks.Download figure: Standard image

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Figure 16 demonstrate the results of applying the full and partial circle cut to wafers with wafer level capped inertial sensors. The cap wafer is glass frit bonded. The glass frit material cannot be printed due to the real outer edge of the cap wafer resulting in an unbonded edge zone, which causes flying cap chips in the dicing process (see Fig. 14). The flying chips lead to dicing blade breakage during chip dicing, which is a serious technical and economic issue. By applying a full circle cut process after the wafer bonding, all potentially loose caps are removed in this process, and at the new wafer edge no flying chips occur, as seen in Fig. 16 (left). In this case the wafer diameter was reduced from 150 mm to 136 mm. The circle cut removed 7 mm, but this is not relevant for the chip yield since the edge exclusion zone from the system wafer process is 10 mm. In the left part of the figure this can be seen as well: at the new wafer edge there are still some blind chips without bond pad openings. The right part of Fig. 16 shows a partial wafer cut on the same kind of wafer. Here, the critical main part of the unbonded edge is removed, and it is clearly seen that the system wafer has still the full diameter. When removing the unbonded areas of the wafer edge by partial circle cutting the risk of dicing blade damages is reduced related to the actual singulation dicing without any circle cutting. Large and especially less pieces of silicon are cut and flying off, this reduces the number of impacts to the blade and even more important thicker and more stable dicing blades can be used, since they are not cutting into the dicing street, where the dicing cut should be as small as possible to have lowest dicing area consumption (costs saving aspect). With this circle cut approach, a very stable production process can be developed, avoiding dicing issues.

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Figure 16. Results of full circle cut at cap wafer bonded inertial sensor wafer, left full circle cut, right partial circle cut (system wafer still with full diameter).Download figure: Standard image

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Glass frit wafer bondingSo far in this paper, mechanical aspects of poorly bonded wafer edges and related risks and problems in the wafer process are discussed. For the example of glass frit bonding, it will be shown now, that the influence of the wafer edge can also have effects on the chip yield in the wafer bonding process. The glass frit bonding process

is based on a low melting point glass, which is screen-printed as a paste typically onto cap wafers, fired to transfer the paste back into a glass, and bonded to the system wafer by heating up to the wetting temperature of the glass. On cooling down, a strong, hermetic bond is formed. Hermeticity is a big benefit of the glass frit bonding, and therefore was intensively investigated. In these investigations

12,13

it was found that hermeticity issues often occur at the wafer edge, not all around, but typically at the left and and/or right side of wafers as shown in Fig. 17.

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Figure 17. Non hermetic chips after glass frit bonding in two different applications with different chip sizes.Download figure: Standard image

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Detailed investigations have shown that the root cause of these non-hermeticities close to the wafer edge is in the screen-printing process. Also, in screen-printing the wafer edge is a zone of discontinuity, but this is overlaid with the printing direction. At screen-printing a squeegee presses the glass frit paste through a structured mesh (screen) onto the wafer. The squeegee travels linearly over the mesh and the wafer. In the center of the wafer there is always sufficient material since it is a continuous soft roll of material. However, at the end of the squeegee, it is possible that there is not enough paste material or it is not continuously pressed through the mesh. This results in open or insufficiently high bonding frames which are not good enough for hermetic bonding, because the required glass material is not fully available to close all gaps. Therefore, it is necessary to do screen- printing with a squeegee significantly longer in relation to the wafer diameter, and with enough screen-printing paste, as illustrated in Fig. 18.

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Figure 18. Screen printing: general principle and wafer edge effects related to squeegee length and amount of print material (paste).Download figure: Standard image

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However, screen printing up to the wafer edge is also with this measure very difficult, since there are even more critical aspects, like the flatness of the machined wafer bed the wafer lays in for screen-printing or screen stretching effects. Therefor it is very important to use perfect bonding condition in the glass frit bonding process. The bonding temperature must bee high enough to allow the wetting of the system wafer and some amount of glass frit flowing. Bond tool pressure need to be high enough, to bring the wafers into contact also at the wafer edge, but also low enough to prevent an uncontrolled glass flowing. This optimization is tricky and need to be done for very wafer layout.Another very special aspect of the glass frit wafer bonding is the thickness of the glass frit bond layer of about 10 to 15 micrometers. This actually forms a significant gap between the two bonded wafers at the area without glass frit. This is often the case at the wafer edge, as the left part of Fig. 19 shows. At this gap, wet chemicls and rinsing water can be trapped and later uncontrolably released, which is always a critical tool or box contamination concern. Typically, the chip structures of the bonding frame are continued up to the wafer edge with the same width the chip bond frames have. Wider structures at the wafer edge are not possible, because they would be printed thicker than the chip bond frames, which would result in non-hermetic product dies or even flying caps at dicing. Hence, suitable edge sealing must be considered in the glass frit layout. Multiple glass frit seal rings at the wafer edge were found to be a good option. At least 2 or, better, 3 are needed for good sealing (Fig. 19 right part) because at the outer edge of the wafer there are the effects of uncontrolled areas due to the edge bead removal (see Fig. 13) and the screen-printing process is difficult, as mentioned. Therefore, the outer edge might have some defects which are closed by the inner seal rings. Here, the design and process need to be optimized to get the best solution.

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Figure 19. Options for screen printing layouts at the wafer edge.Download figure: Standard image

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ConclusionsIt can be concluded that the wafer edge is a zone of discontinuities, causing problems during wafer bonding. If the bonding problems at the edge are understood, they can be solved efficiently by suitable countermeasures. Therefore, to establish these countermeasures, the bonding applications first have to be distinguished. For bonding engineered substrates such as cavity SOI wafers, engineering the wafer edge before the bonding process seems to be the best solution. With unsymmetrical wafer edge profiles bonding close to the wafer edge can be achieved. Edge recessing by etching seems to be easier than edge trimming after bonding, and it does not induce mechanical damage at the wafer edge, which is a critical zone for breakage initiation. For cap wafer bonding, treatment of the edge after wafer bonding to remove unbonded areas is recommended. Bonding of processed wafers up to the wafer edge is very difficult or even impossible, because the wafer edge is unavoidably damaged, related to the edge bead removal. Processing of bonding layers, such as glass frit or metals, up to the wafer edge is not possible. For bonded cap wafer stacks, partial or full circle cuts are effective for defining the wafer edge after bonding. The discussions of edge effects related to wafer bonding are not complete, and every bonding process and every application has its own requirements and specialties, but for industrial wafer bonding processes, the wafer edge must be considered and investigated to achieve a safe, stable wafer bonding process. This is important for both the bonding process and the bonding layer layout. Some aspects are discussed in this paper and should provide a guide towards solutions in other wafer bonding applications.AcknowledgmentsThe Authors would like to thank Dr. Stefan Svoboda Schmalkalden University of Applied Sciences for performing the wafer edge investigations by 3D optical microscopy, Harald Kraffert X-FAB Erfurt for the cross-section analyses and Sebastian Wolf X-FAB Erfurt for optimizing and realizing the special circle cut processes. Roy Knechtel especially thanks the Carl-Zeiss-Foundation for the funding the research activities of his professorship.

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Silicon Wafer Processing

Deren Yang5, Xingbo Liang6 & Xuegong Yu5

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First Online: 28 November 2023

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AbstractThis chapter reviews the Si wafer-processing technology, including ingot heat treatment, cutting, slicing, lapping, polishing, wafer cleaning, and packaging. The ingot heat treatment is used to eliminate thermal donors or repair neutron irradiation damage. After the crystal orientation of Si ingot is measured by X-ray diffraction method, the wafer-making processes start. Nowadays, the blade cutting is gradually replaced by the more efficient wire sawing technology. Then, the lapping is used to remove the damage layer caused by slicing process. The most important step is the wafer polishing, for achieving “mirror like” surface with excellent geometric accuracy for device fabrication. Wafer cleaning is needed to eliminate the contamination during the former processes, followed by the wafer packaging.KeywordsHeat treatmentCrystal orientationCutting technologySlicing technologyLapping technologyPolishing technologyWafer cleaningWafer packaging

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Download referencesAuthor informationAuthors and AffiliationsState Key Lab of Silicon Materials, Zhejiang University, Hangzhou, ChinaDeren Yang & Xuegong YuQl Electronics Co., Ltd., Ningbo, ChinaXingbo LiangAuthorsDeren YangView author publicationsYou can also search for this author in

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Deren Yang .Editor informationEditors and AffiliationsInstitute of Microelectronics, Peking University, Beijing, ChinaYangyuan Wang GTA Semiconductor Co., Ltd., Shanghai, ChinaMin-Hwa Chi School of Software and Microelectronics, Peking University, Beijing, ChinaJesse Jen-Chung Lou Peng Cheng Laboratory, Shenzhen, Guangdong, ChinaChun-Zhang Chen Rights and permissionsReprints and permissionsCopyright information© 2024 Publishing House of Electronics Industry About this entryCite this entryYang, D., Liang, X., Yu, X. (2024). Silicon Wafer Processing.

In: Wang, Y., Chi, MH., Lou, J.JC., Chen, CZ. (eds) Handbook of Integrated Circuit Industry. Springer, Singapore. https://doi.org/10.1007/978-981-99-2836-1_75Download citation.RIS.ENW.BIBDOI: https://doi.org/10.1007/978-981-99-2836-1_75Published: 28 November 2023

Publisher Name: Springer, Singapore

Print ISBN: 978-981-99-2835-4

Online ISBN: 978-981-99-2836-1eBook Packages: EngineeringReference Module Computer Science and EngineeringShare this entryAnyone you share the following link with will be able to read this content:Get shareable linkSorry, a shareable link is not currently available for this article.Copy to clipboard

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比特派10官网下载|wafers

比特派10官网下载|wafers

高科技之半导体硅片概念硅片（又称晶圆、wafer）是光伏、半导体行业广泛使用的基础材料。其中，适用于集成电路行业的是半导体级的硅片半导... - 雪球

WAFER中文(繁體)翻譯：劍橋詞典

wafers是什么意思_wafers的翻译_音标_读音_用法_例句_爱词霸在线词典

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The wafer - Waferfabrication - Semiconductor Technology from A to Z - Halbleiter.org

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The Importance of Wafer Edge in Wafer Bonding Technologies and Related Wafer Edge Engineering Methods - IOPscience

Silicon Wafer Processing | SpringerLink

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比特派10官网下载|wafers

比特派10官网下载|wafers

高科技之半导体硅片 概念 硅片（又称晶圆、wafer）是光伏、半导体行业广泛使用的基础材料。其中，适用于集成电路行业的是半导体级的硅片 半导... - 雪球

WAFER中文(繁體)翻譯：劍橋詞典

wafers是什么意思_wafers的翻译_音标_读音_用法_例句_爱词霸在线词典

Page restricted | ScienceDirect

Attention Required! | Cloudflare

The wafer - Waferfabrication - Semiconductor Technology from A to Z - Halbleiter.org

Page restricted | ScienceDirect

The Importance of Wafer Edge in Wafer Bonding Technologies and Related Wafer Edge Engineering Methods - IOPscience

Silicon Wafer Processing | SpringerLink

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高科技之半导体硅片概念硅片（又称晶圆、wafer）是光伏、半导体行业广泛使用的基础材料。其中，适用于集成电路行业的是半导体级的硅片半导... - 雪球